这些中断用于多种不同任务：内核到MCU的中断用于唤醒MCU执行固件初始化、配置命令流和命令流组、电源管理任务等。MCU到内核的中断通常在内核请求处理完成后使用。用户空间到MCU的中断用于告诉GPU开始处理一组命令流指令。GPU到MCU的中断可能在命令流处理完成时发生。MCU定时器中断可用于在设定时间后运行代码。
Furthermore, the critical path of the PIO core is at least 2x worse than that of the VexRiscv. The FPGA design easily closes timing at 100MHz with just the VexRiscv, but with the PIO core in place, it struggles to close timing at 50MHz.
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